exception n. 1.例外;除外,除去。 2.【法律】抗告;異議,不服,反對(duì)。 Every rule has its exceptions. 任何規(guī)則均有例外。 by way of exception 作為例外。 liable [subject] to exception 容易遭到反對(duì)的,會(huì)引起異議的。 make an exception of 把…作為例外。 make no exceptions 一視同仁,一樣看待。 take exception 1. 反對(duì),表示異議。 2. 有反感。 take exception at 發(fā)怒,生氣。 take exception to [against] 對(duì)…提出異議。 without exception 一概,全都;無(wú)例外地。 with the exception of 除…外。 adv. -ally ,-less adj. 無(wú)例外的。
Shows event exception processing for deadlocks 展示了針對(duì)死鎖的事件異常處理。
Exception processing is monitoring for those situations which indicate an abnormal problem , or an unusual situation that warrants attention from the dba 異常處理是對(duì)那些會(huì)指出反常問題的狀況或者值得dba注意的不尋常狀況的監(jiān)控。
If an exception process occurs or can t complete the transaction with any one of the third party providers , the web service has to make sure to go back to the previous state 如果發(fā)生異常事件或是不能與任一個(gè)第三方完成事務(wù), web服務(wù)必須保證能回到前一個(gè)狀態(tài)。
A series of basic functions are performed in the chapter 4 , includes microengine initialization , packet receive processing , exception process , mac and ip header processing , ip forwarding , and packet transmit processing , etc . these functions build a basic data path for the whole system 第四章中實(shí)現(xiàn)一系列最基本的功能,包括微引擎初始化,包接收處理,異常處理, mac及ip頭部處理, ip轉(zhuǎn)發(fā)以及包發(fā)送處理等。這些功能為整個(gè)系統(tǒng)建立起一條基本的數(shù)據(jù)通路。
The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu , and dwells on 64 - bit vega cpu characteristic , and details the eda technology and the main flow of asic design , and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation , and details cache architecture and mmu . the master dissertation dwells on virtual address translating into physical address , instruction cache finding address and instruction fetching , too 詳細(xì)的闡述了64位vegacpu的特點(diǎn),闡述了eda技術(shù)和asic設(shè)計(jì)的主要流程,闡述了vegacpu流水線結(jié)構(gòu)、流水線操作、流水線暫停和異常處理,虛擬指令地址的結(jié)構(gòu)和產(chǎn)生, mmu結(jié)構(gòu),包括指令tlb結(jié)構(gòu)和虛擬指令地址向物理指令地址的生成流程, cache結(jié)構(gòu),尋址原理和指令的寫策略,指令高速緩存的尋址原理和結(jié)構(gòu),以及指令的獲取流程。